Method of assembling microelectronic package and method of operating the same
US11315916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Sep 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.