Circuit for controlling a stacked snapback clamp
US11315919B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 2019 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jul 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/815
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is formed on a substrate, and the integrated circuit includes first and second conductors for providing supply and ground voltages, respectively, a clamp device, and a trigger circuit. The clamp device includes first and second metal oxide semiconductor (MOS) transistors coupled in series between the first and second conductors, wherein the first and second MOS transistors include first and second gates, respectively. The trigger circuit is coupled between the first and second conductors and is configured to drive the first and second gates with first and second voltages, respectively, in response to an electrostatic discharge (ESD) event. The trigger circuit includes a biasing circuit for generating the first voltage as a function of the supply voltage, a PMOS transistor coupled between the first conductor and the second gate, wherein the PMOS transistors includes a third gate. The trigger circuit also includes a resistive element coupled between the first conductor and the third gate, and a capacitive element coupled between the third gate and the first gate. In one configuration a voltage at the third gate should decrease in response to activation of the se…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.