Integrated circuit with anti-punch through control
US11315921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2019 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jan 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.