LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods

US11316044B2 · kind B2 · utility

Assignee

• Maxim Integrated Products, Inc. · US

Inventors

• Tom K. Castro · Santa Clara, US
• Rajwinder Singh · Pleasanton, US
• Badredin Fatemizadeh · Sunnyvale, US
• Adam Brand · Palo Alto, US
• John Xia · Fremont, US
• Chi Nung Ni · Foster City, US
• Marco A. Zuniga · Berkeley, US

Key dates

• Filing date: Jun 5, 2018
• Grant date: Apr 26, 2022
• Expiry date: Jun 5, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/126

Abstract

A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.