Skyrmion stack memory device
US11316099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Aug 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N52/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory stack formed on a substrate to program skyrmions within at least one layer of the stack. The skyrmions represent logic states of the memory device. The memory stack further includes a top and bottom electrode to receive electrical current from an external source and to provide the electrical current to the memory stack. A free layer stores a logic state of the skyrmions in response to the electrical current. A Dzyaloshinskii-Moriya (DM) Interaction (DMI) layer in contact with the free layer induces skyrmions in the free layer. A tunnel barrier is interactive with the DMI layer to facilitate detection of the logic state of the skyrmions in response to a read current. At least one fixed magnetic (FM) layer is positioned within the memory stack to facilitate programming of the skyrmions within the free layer in response to the electrical current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.