Input voltage endurance protection architecture
US11316483B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2019 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jan 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/441
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is an input voltage endurance protection architecture applied to a high-voltage operational amplifier with high input amplitude and high linearity. The input voltage endurance protection architecture includes three parts: a main operational amplifier, an auxiliary operational amplifier and an input stage voltage endurance protection circuit. The main operational amplifier is a high-voltage general-purpose operational amplifier, the auxiliary operational amplifier is a single-stage differential amplifier, and the single-stage differential operational amplifier is connected to a degeneration resistor Rbias. In addition, the auxiliary operational amplifier has a same connection method as the main operational amplifier at a positive input terminal and a negative input terminal, and both the positive input terminal and the negative input terminal are protected by an input stage voltage endurance protection circuit and receive and process input signals simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.