Process independent spread spectrum clock generator utilizing a discrete-time capacitance multiplying loop filter
US11316524B1 · kind B1 · utility
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17Claims
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Key dates
| Filing date | Dec 2, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Dec 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/69
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a spread spectrum clock generator, comprising a digital delta sigma modulator coupled to a fractional N, phase locked loop (PLL), the PLL comprising a discrete-time capacitance multiplier loop filter, the discrete-time capacitance multiplier loop filter comprising: an amplifier comprising a non-inverting input and an inverting input; a first switched capacitor resistor and a capacitor coupled to the non-inverting input, the capacitor coupled between the first switched capacitor resistor and the non-inverting input; and a second switched capacitor resistor coupled to the inverting input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.