Method, device, and computer program for improving synchronization of clocks in devices linked according to a daisy-chain topology
US11316605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2017 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Oct 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0641
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method for synchronizing a logical clock in a device comprising a physical clock, an input port, and an output port, the device further comprising a logical clock and a time compensation clock sharing the physical clock, the time compensation clock making it possible to determine a residence time, comprising obtaining a theoretical residence time, during a pre-synchronization phase according to which the logical clock is not synchronized, adding a value representative of the obtained theoretical residence time to a residence time value stored in a synchronization message to be forwarded, during a synchronization phase according to which the logical clock is synchronized, obtaining a residence time and adding a value representative of the obtained residence time to a residence time value stored in a synchronization message to be forwarded, and synchronizing the logical clock as a function of a residence time value stored in a received synchronization message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.