Tensor-based memory access
US11321092B1 · kind B1 · utility
16Cited by
11References
22Claims
0Family size
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Key dates
| Filing date | Oct 25, 2018 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Feb 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes an internal memory and processing circuitry. The internal memory is configured to store a definition of a multi-dimensional array stored in an external memory, and indices that specify elements of the multi-dimensional array in terms of multi-dimensional coordinates of the elements within the array. The processing circuitry is configured to execute instructions in accordance with an Instruction Set Architecture (ISA) defined for the processor. At least some of the instructions in the ISA access the multi-dimensional array by operating on the multi-dimensional coordinates specified in the indices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.