Memory device and memory module including same
US11321177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Dec 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.