Multi-chip system and cache processing method
US11321233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Jul 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-chip system and a cache processing method are provided. The multi-chip system includes multiple chips. Each chip includes multiple clusters, a crossbar interface, and a snoop system. Each cluster corresponds to a local cache. The crossbar interface is coupled to the clusters and a crossbar interface of another chip. The snoop system is coupled to the crossbar interface and performs unidirectional transmission with the crossbar interface. The snoop system includes a snoop table module and multiple trackers. The snoop table module includes a shared cache, which records a snoop table. Multiple trackers are coupled to the snoop table module, query the snoop table in the shared cache according to a memory access request initiated by one of clusters, and update the snoop table according to a query result. The snoop table corresponds to a storage structure of the local cache corresponding to the clusters in all chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.