Computing system for transmitting completion early between serially connected electronic devices
US11321254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Aug 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/2806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system includes a host, a first electronic device including a memory and an accelerator, and a second electronic device including a direct memory access (DMA) engine. Based on a command transmitted from the host through the first electronic device, the DMA engine transmits data and completion information of the command to the first electronic device. The memory includes a data buffer storing the data and a completion queue buffer storing the completion information. The accelerator executes a calculation on the data. The DMA engine transmits the data to the first electronic device and then transmits the completion information to the first electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.