Hardware secure element, related processing system, integrated circuit, device and method
US11321492B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 30, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Nov 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/127
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.