Patent · US Active

Macro clock latency computation in multiple iteration clock tree synthesis

US11321514B1 · kind B1 · utility

1Cited by

0References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Dirk Meyer · Frankfurt, DE
Ben Thomas Beaumont · Oakington, GB
Zhuo Li · Austin, US

Key dates

Filing date	Dec 31, 2020
Grant date	May 3, 2022
Priority date	—
Expiry date	Dec 31, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Aspects of the present disclosure address systems and methods for clock tree synthesis (CTS). A first iteration of CTS is performed to generate an intermediate clock tree for an integrated circuit (IC) design that includes one or more macros. Target pin insertion delays (PIDs) for the one or more macros are computed based on the intermediate clock tree using a linear program. A second iteration of CTS is performed using the target PIDs for the one or more macros to generate an optimized clock tree for the IC design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.