Bit-line voltage generation circuit for a non-volatile memory device and corresponding method
US11322201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2021 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Jan 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.