Class-D amplifier which can suppress differential mode power noise
US11323082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Aug 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/459
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.