Glitch filter system
US11323106B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Nov 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.