High-speed multiplexer
US11323115B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2021 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | May 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/6878
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed multiplexor comprises a set of differential input pairs to receive and mix a set of differential input signals at a differential output node pair. The high-speed multiplexer further comprises an active inductive load pair driven by the input stage using the mixed set of differential input signals. Each active inductive load comprises a p-channel field effect transistor (pFET) device connected to one of the differential output node pairs and a resistor connected between a gate node and a drain node of the pFET device. The multiplexer further comprises a first cross-coupling capacitor connected between the gate node of a first inductive load and a second output node of the differential output node pair and a second cross-coupling capacitor connected between the gate node of a second inductive load and a first output node of the differential output node pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.