Programmable device structure based on mixed function storage unit
US11323121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2018 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Mar 7, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable device structure based on a mixed function storage unit includes a storage unit SRAM and a mixed function unit, wherein the storage unit comprises n register units and at least one selection control bit, wherein n=2{circumflex over ( )}x, and x is natural number; the register units are selected according to the selection control bit; and when the selection control bit selects the mixed function unit to serve as a lookup table, a logic function is achieved; or when the selection control bit selects the mixed function unit to serve as a multiplexer, a routing function is achieved. By multiplexing the register units, the programmable device structure achieves a routing function of a traditional FPGA and also provides a logic function, and the waste of resources is greatly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.