Circuit for generating multi-phase clock having random disturbance added thereto

US11323129B2 · kind B2 · utility

Assignee

• NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION · CN

Inventors

• Jie Pu · Pforzheim, DE
• Gangyi Hu · Chongqing, CN
• Dongbing Fu · Chongqing, CN
• Zhengping Zhang · Chongqing, CN
• Liang Li · Beijing, CN
• Ting Li · Nan'an District, CN
• Daiguo Xu · Chongqing, CN
• Mingyuan Xu · Chongqing, CN
• Xiaofeng Shen · Nanhu, CN
• Xianjie WAN · Chongqing, CN
• Youhua Wang · Chongqing, CN

Key dates

• Filing date: Dec 13, 2018
• Grant date: May 3, 2022
• Expiry date: Dec 13, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M1/0624
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.