Delay-based spread spectrum clock generator circuit
US11323131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Nov 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3022
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.