Decision feedback equalization training scheme for GDDR applications
US11323296B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Nov 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0349
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The embodiments described herein provide for a method and system for training an optimal decision feedback equalization (DFE) coefficient for use in GDDR and DDR applications. The method includes determining a first expected bit pattern using a reference voltage. The method further includes determining a transition voltage value of the first expected bit pattern. The method further includes receiving a second expected bit pattern having a same first bit as the first expected bit pattern. The method further includes determining a transition voltage value of the second expected bit pattern using the reference voltage. The method further includes calculating an optimal reference voltage value by averaging the transition voltage values of the first expected bit pattern and the second-expected bit pattern and storing the optimal reference voltage value in a register corresponding to a logic value of the same first bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.