Capacitive compensation for vertical interconnect accesses
US11324119B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Oct 23, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.