Method and apparatus for eliminating bit disturbance errors in non-volatile memory devices
US11327882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2020 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Sep 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.