Method and system for facilitating communication between interconnect and system memory on system-on-chip
US11327908B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 2020 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Jul 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory management system for facilitating communication between an interconnect and a system memory of a system-on-chip includes a plurality of memory controllers coupled with the system memory, and processing circuitry coupled with the interconnect and the plurality of memory controllers. The processing circuitry is configured to receive a transaction request from the interconnect, and identify a memory controller of the plurality of memory controllers that is associated with the received transaction request. Further, the processing circuitry is configured to provide the transaction request to the identified memory controller for an execution of a transaction associated with the received transaction request. The processing circuitry is further configured to receive a transaction response to the provided transaction request from the memory controller, and provide the received transaction response to the interconnect after a previous transaction response associated with a previous transaction request is provided to the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.