Processor element redundancy for accelerated deep learning
US11328208B2 · kind B2 · utility
11Cited by
41References
41Claims
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Key dates
| Filing date | Aug 27, 2019 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Aug 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/088
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques in advanced deep learning provide improvements in one or more of cost, accuracy, performance, and energy efficiency. The deep learning accelerator is implemented at least in part via wafer-scale integration. The wafer comprises a plurality of processor elements, each augmented with redundancy-enabling couplings. The redundancy-enabling couplings enable using redundant ones of the processor elements to replace defective ones of the processor elements. Defect information gathered at wafer test and/or in-situ, such as in a datacenter, is used to determine configuration information for the redundancy-enabling couplings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.