Ternary content addressable memory based on memory diode
US11328774B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2018 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Jul 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses a ternary content addressable memory based on a memory diode, which includes a plurality of kernel units having functions of storing data, erasing/writing data, and comparing data; the kernel units are arranged in an array, all kernel units in a unit of row are connected to a same matching line, and all kernel units in a unit of column are connected to a same pair of complementary search signal lines; the kernel unit includes two memory diodes; top electrodes of a first memory diode and a second memory diode are respectively connected to a pair of complementary search signal lines, and bottom electrodes of the first memory diode and the second memory diode are connected to a same matching line. The present disclosure can greatly reduce a chip dimension of the ternary content addressable memory and reduce power consumption; the ternary content addressable memory of the present disclosure has a simple structure, which effectively simplifies a manufacturing process and reduces a manufacturing cost; the present disclosure provides and achieves a memory diode that is compatible with a standard CMOS process, which is suitable for currently rapidly develop…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.