SRAM device and manufacturing method thereof

US11329056B2 · kind B2 · utility

Assignee

• Powerchip Semiconductor Manufacturing Corporation · TW

Inventors

• Shou-Zen Chang · Taipei, TW
• Yi-Hsung Wei · Taoyuan, TW
• Jia-You Lin · Hsinchu, TW
• Pei-Hsiu Tseng · Tainan, TW
• Chih-Peng Lee · New Taipei, TW
• Chi-Wei Lin · Jinshanmian, TW

Key dates

• Filing date: Jul 16, 2020
• Grant date: May 10, 2022
• Expiry date: Aug 28, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/5228
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A SRAM device includes a substrate, at least one two-transistor static random access memory (2T-SRAM), an inner dielectric layer, a plurality of contacts, an inter-layer dielectric (ILD) layer, a plurality of vias, and a conductive line. The 2T-SRAM is disposed on the substrate, the inner dielectric layer covers the 2T-SRAM, and the contacts are disposed in the inner dielectric layer and coupled to the 2T-SRAM. The ILD layer covers the inner dielectric layer and the contacts, and the vias are disposed in the ILD layer and respectively coupled to the 2T-SRAM trough the corresponding contacts. The conductive line is disposed on the ILD layer and connects with the plurality of vias, wherein the thickness of the conductive line is less than or equal to one-tenth of the thickness of the via such that it can significantly reduce the coupling effect compared with the traditional bit line.