Two-terminal biristor with polysilicon emitter layer and method of manufacturing the same
US11329157B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Aug 20, 2019 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Sep 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.