Preventing sub-harmonic oscillation with clock delay compensation, in a DC-DC switching converter
US11329561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2020 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Oct 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The clock input of a buck converter is delayed, preventing sub-harmonic oscillation. The function may be achieved by implementing a clock delay generation circuit, configured to delay a next clock pulse by an amount of time directly proportional to the most recent on time of the high-side switch for peak-mode current control, inversely proportional to the most recent on time of the low-side switch for peak-mode current control, inversely proportional to the most recent on time of the high-side switch for valley-mode current control, or inversely proportional to the clock minus the most recent on time of the high-side switch for valley-mode current control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.