Delay circuit of delay-locked loop circuit and delay-locked loop circuit
US11329654B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2021 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Jan 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.