Frequency synthesiser circuits
US11329656B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2019 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Dec 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesiser arrangement is arranged to receive a clock input signal and provide an output signal. The frequency synthesiser arrangement comprises: a frequency divider arranged to divide the output signal by a variable number N and output a feedback signal; a phase detector arranged to detect a phase difference between the feedback signal and the clock input signal; a phase alignment circuit portion arranged to determine an overlap of the clock input signal and the feedback signal; and a voltage controlled oscillator which is arranged to receive either a first input derived from the phase detector or a second input from an external reference voltage and to provide the output signal. The phase alignment circuit portion is arranged to provide a control output which determines whether the voltage controlled oscillator receives the first or second input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.