Patent · US Active

Network-on-Chip topology generation

US11329690B2 · kind B2 · utility

0Cited by

5References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Narayana Sri Harsha Gade · Bengaluru, IN
Honnahuggi Harinath Venkata Naga Ambica Prasad · Bengaluru, IN
Anup Gangwar · Bengaluru, IN
Nitin Agarwal · Bengaluru, IN
Ravishankar Sreedharan · Bengaluru, IN

Key dates

Filing date	Feb 9, 2021
Grant date	May 10, 2022
Priority date	—
Expiry date	Feb 9, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH04L47/125
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

The present disclosure provides computer-based methods and a system for synthesizing a NoC that advantageously generate balanced NoC topologies without end-to-end fairness or local credit-based arbitration, and improve NoC performance when destination device bridge ports support only one incoming physical link per channel. More particularly, a clock domain is assigned to certain routers that satisfies the minimum frequency for the router while reducing clock domain transitions to neighboring routers, and the traffic flows received by these routers are balanced based on the traffic flow packet rates.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.