Voltage sampling circuit and method for sampling voltage
US11333713B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Sep 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/388
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A voltage sampling circuit is provided for sampling voltage of at least two sets of cells in a battery pack includes at least two analog front ends including a low-side analog front end connected to a first set of cells and a high-side analog front end connected to a second set of cells, a subtractor has a positive input end and a negative input end, the positive input end connecting to the output of the high-side analog front end for receiving the analog voltage output by the high-side analog front end. When the first set of cells is connected with the second set of cells in series, the negative input end of the subtractor connecting to the total positive the first set of cells, when the first set of cells is connected with the second set of cells in parallel, the negative input end of the subtractor is grounded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.