Processing system and control method wherein a microprocessor configured to set a plurality of memories into a self-refresh mode and a main processor in a standby mode
US11334143B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Jul 11, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes random access memory, memories, a main processor, and a microprocessor. The random access memory is configured to store code. The main processor is configured to transfer the code to a first memory in the memories. The microprocessor is configured to set the memories into a self-refresh mode and turn off the main processor in a standby mode. The microprocessor generates a first command based on a predetermined event, in which the main processor is further configured to be activated according to the first command, in order to enable the first memory. The microprocessor executes a standby application according to the code stored in the first memory, in order to confirm whether to operate in the standby mode constantly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.