Method and apparatus for isolating a memory
US11334291B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Mar 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a method and device are disclosed. In an embodiment, a controller includes a plurality of memories each having registers that are accessible using an address, a plurality of memory controllers each coupled to a memory and configured to control read and write operations to the respective coupled memory, a bus coupled to each of the memory controllers configured to communicate data and commands to each of the memory controllers, a plurality of processing cores coupled to the bus and configured to read and write data to the memories through the memory controllers, and a plurality of isolation stages, each isolation stage being coupled between a memory controller and a memory and configured to isolate the respective memory from receiving a memory clock signal when the memory is not addressed by the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.