Integrated circuit facilitating subsequent failure analysis and methods useful in conjunction therewith
US11334447B2 · kind B2 · utility
0Cited by
5References
14Claims
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Assignee
Inventor
Key dates
| Filing date | Aug 27, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Aug 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chip aka integrated circuit, the chip comprising configuration register/s, typically volatile, and/or at least one on-chip non-volatile memory m typically including at least one reserved memory location, which may be reserved for storing contents of at least one typically volatile configuration register r, from among the configuration registers; and/or apparatus configured for, at least once, storing values which may be indicative of content of at least one typically volatile configuration register r from among the registers, e.g. in the on-chip non-volatile memory m, e.g. at the at least one reserved memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.