Patent · US Active

Method and apparatus for redundant data processing in which there is no checking for determining whether respective transformations are linked to a correct processor core

US11334451B2 · kind B2 · utility

0Cited by

8References

15Claims

0Family size

Assignee

Siemens Mobility GmbH · DE

Inventors

Uwe Eckelmann-Wendt · Wolfenbüttel, DE
Stefan Gerken · Braunschweig, DE

Key dates

Filing date	Jul 24, 2017
Grant date	May 17, 2022
Priority date	—
Expiry date	Sep 30, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2201/845
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An arrangement for redundant data processing has an integrated circuit in which the functionality of a multi-core processor is implemented. Processor cores (40; 50) of the multi-core processor are each designed to execute a useful program. The results which emerge from the execution of the useful program by the different processor cores are compared by a comparison module of the arrangement. The processor cores differ from one another with respect to an address or data structure (AS1, AS2; DS1, DS2) which is used by a processor core to respectively store and read data in or from a memory area (70; 80) that is assigned to the particular processor core. In terms of hardware, the individual processor cores are at least partially implemented separately in the integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.