Semiconductor memory device and memory system including the same
US11334457B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Nov 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.