Side cache array for greater fetch bandwidth
US11334491B1 · kind B1 · utility
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1References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 18, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Jan 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a microprocessor, comprising: an instruction cache configured to receive an instruction fetch comprising a first byte portion and a second byte portion; a side cache tag array configured to signal further processing of the second byte portion in addition to the first byte portion based on a hit of the side cache tag array; and a side cache data array configured to store instruction data for the second byte portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.