Cache securing method and device capable of resisting side channel attack
US11334668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2018 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Jun 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a device for securing a cache against side channel attacks are provided. An allocator identifier ALLOCATOR field is added to each cache entry in the present disclosure. Whenever an entry is allocated in the cache, the identifier of the software domain currently running on the processor is filled into the ALLOCATOR field of the allocation entry. When accessing the cache, the cache entry can be hit only if the identifier of the software domain currently running on the processor is identical to the ALLOCATOR field in the cache entry. If the cache entry to be replaced is invalid or its ALLOCATOR field is identical to the identifier of the software domain currently running on the processor, then the existing entry in the cache is replaced directly; otherwise, the entire cache is emptied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.