In-memory computing circuit for fully connected binary neural network
US11335387B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2019 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Jan 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.