Semiconductor memory device including memory string and plurality of select transistors and method including a write operation
US11335388B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Apr 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device, in a write operation performed to a memory cell transistor, a first voltage is applied to a first word line and a second voltage lower than the first voltage is applied to a second word line. When a command to stop is received during the write operation, a third voltage lower than the second voltage is applied to the first and second word lines, thereafter a fourth voltage higher than the third voltage is applied to a first selection line, thereon or thereafter a fifth voltage higher than the fourth voltage is applied to the first and second word lines, thereafter a sixth voltage lower than the fourth voltage is applied to the first selection line, and thereafter a seventh voltage is applied to the first and second word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.