Memory test circuit
US11335427B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Nov 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.