Via hole structure, manufacturing method thereof, electronic device, and display device
US11335625B2 · kind B2 · utility
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1References
19Claims
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Key dates
| Filing date | Dec 16, 2019 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Jan 16, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/04164
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A via hole structure includes: a first conductive layer, an interlayer insulating layer, and a second conductive layer that are sequentially arranged, wherein the interlayer insulating layer is provided with a via hole, the second conductive layer is overlapped with the first conductive layer by the via hole, and at least part of a surface, in contact with the second conductive layer, of the interlayer insulating layer is uneven.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.