Low impedance multi-conductor layered bus structure with shielding
US11335649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Aug 1, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Various embodiments of laminated planar bus structures that minimize electromagnetic interference (EMI) and parasitic inductance are described. In one embodiment, a laminated planar bus structure may include a plurality of stacked conductive layers and a plurality of stacked insulation layers. The plurality of stacked conductive layers may include positive and negative conductive layers, and conductive ground layers stacked as outer layers as to enclose vertically the positive and the negative conductive layers. In another embodiment, the laminated planar bus structure may include a middle ground layer stacked in between the positive and the negative conductive layers to provide additional reduction in electric field strength. A laminated planar bus structure that is integrated with other power electronics components is also presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.