Integrated circuit device
US11335695B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2019 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Mar 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.