Metal oxide semiconductor integrated circuit basic unit
US11335785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Dec 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.