System and method to manage power throttling
US11340673B1 · kind B1 · utility
3Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Oct 21, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.