Power management circuitry for controlling a power state transition based on a predetermined time limit
US11340683B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Nov 14, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and mechanisms for a power management circuit to monitor a power domain during one or more attempts to configure a low power state of the power domain. In an embodiment, the one or more attempts are performed during an instance of a local power state at a processor that is coupled to the power management circuit. The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time. Where the condition is detected, the power management circuit generates one or more signals which change the local power state of the processor, or interrupt an operating system that is executed with the processor. In another embodiment, the power management circuit provides analytic data based on the monitoring of the one or more attempts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.